April 2nd 2008 - At the Intel® Developer Forum (IDF), now in progress in Shanghai, XtremeData™, Altera®, and Intel® Corporation (Nasdaq: INTC) are demonstrating acceleration of a full double-precision floating point simulation of a Monte Carlo financial simulation analysis. This demonstration for the first time combines the Intel® QuickAssist Technology, Altera’s high performance Stratix® III FPGA family, XtremeData’s XD2000 family of In-Socket Accelerators (ISA)™, and the new XtremeRNG™ library of building blocks for random number generation (RNG) to significantly accelerate financial and scientific Monte Carlo applications.

XtremeData and Altera Demonstrate the Power of Intel® QuickAssist Technology and the XtremeRNG Library at the Spring Intel Developer Forum.

Dr. Misha Burich, senior vice president of research and development at Altera: "Altera is working closely with XtremeData to harness the double-precision floating point capabilities of our high performance FPGAs,"

"Altera is working closely with XtremeData to harness the double-precision floating point capabilities of our high performance FPGAs," said Dr. Misha Burich, senior vice president of research and development at Altera. "Stratix III FPGAs offer an almost unlimited flexibility in dataflow architectures and is an ideal solution for our customers in the financial, military and medical markets to implement arithmetic functions or to accelerate a system by off-loading a datapath that cannot be optimally implemented in a stand alone processor."

Monte Carlo simulation of financial instruments consists of three steps: Pathway Generation, Pathway Evaluation, and Expectation/Computation. By combining the power of QuickAssist™ Technology and the XD2000i In-Socket Accelerator, XtremeData demonstrates that source code written within the QuickAssist abstraction framework can be re-targeted between the CPU and the FPGA without modifying the original source code.

The XD2000i™ family is the only accelerator family that successfully applies multiple FPGAs. XtremeData designed the module with three Altera FPGAs, one as a bridge to system resources, and the other two for running user applications. This industry-first design allows user reconfiguration of the application FPGAs in-system, without rebooting the server. This lets system designers focus on getting algorithms working in the application FPGAs without needing to understand and trouble-shoot the system interfaces.

When XtremeData co-processor modules are integrated into commercial, off-the-shelf (COTS) servers, blade systems and ATCA boards, applications can be substantially accelerated via parallelization and pipelining. The XD2000i provides high-performance application acceleration ranging up to 10X versus alternative solutions, while simultaneously reducing overall system power consumption and latency. It is the ideal solution for accelerating applications such as algorithmic financial trading, market data, deep packet inspection, bioinformatics, military and video transcoding.

“The demonstration of Monte Carlo simulation on the XtremeData XD2000i In-Socket Accelerator using Intel QuickAssist Technology showcases a powerful FPGA co-processing solution,” said Dylan Larson, Director, Server Software and Technology Initiatives, Digital Enterprise Group, Intel Corporation. “The Intel QuickAssist Technology Accelerator Abstraction Layer allows customers to maintain a standard code base which can target accelerators, like the XD2000i, or Intel® Xeon® processor at run time.”

Attendees visiting the XtremeData booth BU016 will see a live product demonstration of the XD2000i In-Socket Accelerator directly interfacing to the 64-bit Front-Side Bus (FSB), showcasing that key routines in the simulation can be executed on the Stratix III FPGAs BU016 will see a live product demonstration of the XD2000i In-Socket Accelerator directly interfacing to the 64-bit Front-Side Bus (FSB), showcasing that key routines in the simulation can be executed on the Stratix III FPGAs residing on the ISA, the Xeon, or a combination of both, without changes to the overall application code.

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