Chicago - xCelor LLC has announced a new solution for high-frequency traders. xCelor's MFH product is based on FPGA technology and interfaces with strategy code via the PCIexpress bus. xCelor has made MFH product generally available after working with a client running xCelor's first proof-of-concept cards in a production environment for the past nine months.

xCelor's solution pushes as much of the work as possible down to the card, this includes parsing the UDP multicast feed from the exchange, requesting dropped packets via the TCP channel, feed normalization and, importantly, order book construction. A super-thin user space layer provides the interface into client code - all expensive computation is pushed down into the hardware so system CPUs are free to get on with running clients' trading strategies.

With the MFH's C++ API providing a normalized book to user applications, the same code can run against all four of the major New York market centers with little or no modification.

xCelor offers two flavors of card, both based on Xilinx Virtex 6 FPGA technology. xCelor's 10 Gigabit Ethernet card can provide access to two exchanges on the same card. An entry level 1GE card is also available - providing access to a single exchange.

In tests demonstrated at the FIA trade show in Chicago, xCelor's 1GE Arca card was seen running through 15 minutes' worth of Arca data (approx. 1Gb) in around 35 seconds, with zero jitter - and spare cycles on the FPGA. Average network-to-userspace latency of less than 700ns was observed, measured by counting clock cycles on the card. xCelor's 10GE cards improve on the latency figures even further - with less than 500ns observed latency. The xCelor 1GE MFH has been tested at a sustained packet rate of 400Mbit/sec with zero jitter, and has the capability to handle microbursts at link speed.

xCelor MFH modules for Arca, BATS, DirectEdge and NASDAQ are available for proof-of-concept evaluation now through xCelor LLC. For more information, please contact Robert Walker on +1 (312) 462-0022.

Also coming soon: xCelor's hardware-based Risk Evaluation Module for SEC Rule 15c3-5 compliance. Existing naked-access strategy code can run against xCelor's hardware for near-zero latency 15c3-5 compliance, with synthesized exchange-native reject messages on breach.