The DINI Group has announced the availability of TCP Offloading Engine IP (TOE) specifically targeted for use in FPGA-based low latency networking applications. This specialized IP is provided free of licensing fees as part of the reference design package supplied with DINI Group's FPGA hardware products.

TCP Offloading is a necessary and vital function in high frequency trading (HFT). The DINI Group TOE is targeted for use on the DNPCIe_10G_HXT_LL and the lower cost DNPCIe_10G_K7_LL, FPGA based network hardware that is optimized on every variable for this application. These are GEN2 PCIe-hosted network interface cards (NICs) and feature Xilinx FPGAs. These FPGAs have internal 10 GbE PHYs, eliminating the latencies associated with external PHYs.

Low latency Ethernet packet analysis for high frequency trading (HFT) requires a TOE function to minimize latency caused by network transport protocol. To date, the lack of options for the TOE function has been an obstacle to implementation of FPGA based NICs. The DINI TOE IP uses only a small percentage (-5%) of the FPGA gates. When utilized with DINI FPGA products, every possible variable that affects input to output latency has been analyzed and minimized. Raw 10 GbE Ethernet packets can be analyzed and acted upon without interrupts or an operating system adding delay to the process. This IP and hardware package has the ability to achieve the theoretical minimum Ethernet packet processing latency.

"We have used our experience as FPGA/ASIC design specialists to develop the lowest possible latency for Ethernet packet analysis," says Mike Dini, president. "The board/TOE combination can accomplish input to output latencies on FIX messages of less than five hundred nanoseconds."

The TOE is available as part of the FIX Board Support Package (DN_FBSP) and is restricted to use only on DINI Group FPGA boards. It requires the use of several Xilinx software products, including the 10 GbE MAC. The board and TOE is plug-in compatible with most Linux servers.