Impulse Accelerated Technologies VP Buechner to present at STAC conference on FPGA
First Published Friday, 3rd December 2010 from Automated Trader : Algorithmic Trading News
American accelerated trading software expert to explain methods of FPGA accelerating network interfaces and trading algorithms at Securities and Technology Analysis Center Performance Summit in London on 8th December
David Buechner, VP, Impulse Accelerated Technologies:
“We will inevitability be dealing with 40G and 100G data in the next few years. Processing data in line, off-loading processors and complete hardware trading systems are requisite for that level of network data challenge.”
Impulse Accelerated Technology has announced that David Buechner will present in the STAC Conference on December 8, 2010 at Bank of America Merrill Lynch, 2 King Edward Street, London. The Summit will cover the latest topics related to networks, time synchronization, latency monitoring, middleware, tick databases, and trade execution. Mr. Buechner, a VP at Impulse Accelerated Technologies, will present in the FPGA Realities session.
The panel will address the challenges encountered in hardware based system trading. Mr. Buechner will explain how hardware compiled systems are less impacted by jitter, are deterministic, and how using software programmable hardware network interface cards can reduce or eliminate latency on incoming financial feeds and outgoing trade instructions.
Noting that peak message rates climbed from 100/second in 1992, to nearly 1 million in 2008 and 1.7M by 2010, Mr Buechner comments, "We will inevitability be dealing with 40G and 100G data in the next few years. Processing data in line, off-loading processors and complete hardware trading systems are requisite for that level of network data challenge."
Impulse's CEO, Brian Durwood explained further, "Programming hardware from C actually is a bit of rocket science. Impulse C technology grew from projects at Los Alamos National Labs. The trickle down to computational finance is happening very quickly."
FPGAs are used for algorithmic low latency trading at rates of GigE, 10GigE and 40GigE. An FPGA trading system is built without an operating system, reducing jitter during high market conditions. Running without an O/S creates deterministic, scalable modules. This is because FPGA processing does not require instructions from a central processor; instructions which can add variance to the response time. Impulse tools integrate trading logic processing with embedded TCP/IP stacks on FPGA based platforms.
Impulse makes an optimizing compiler which enables software engineers to offload parallelizable, critical path logic to multiple hardware processors. Impulse C handles the parallelization and the C to hardware conversion automatically. It also creates ModelSim test benches to shorten development time. In addition to Wall Street algorithm developers, Impulse C is used by federal agencies, auto makers, medical imaging manufacturers, Japanese imaging companies and hundreds of R & D labs worldwide. www.Impulsec.com
For more information read the article in Q4 of Automated Trader - Accelerated Automated Trading, which features a discussion with David Buechner, Larry Cohen and Edward Trexel on low-latency automated trading via FPGA-based NICs.
