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Algo-Logic Systems introduces low latency PCIe/DMA FPGA solution

First Published 20th April 2016

PCIe/DMA solution achieves rapid host to FPGA roundtrip latency of under 1 microsecond for the accelerated finance and the datacenter industries.

Santa Clara, California - Algo-Logic Systems, a provider of hardware-accelerated, deterministic, real-time, ultra-low-latency solutions, has announced the release of their latest PCI express (PCIe) with Direct Memory Access (DMA) Gen 3x8 solution for the Accelerated Finance and the Datacenter industries. Algo-Logic's low latency PCIe/DMA solution transfers data between Field Programmable Gate Array (FPGA) logic, processors, and memory.

In many High Frequency Trading (HFT) systems, rapid data transfers are needed between FPGA logic and the Order Management System (OMS) software. For these frequent and short transactions, Algo-Logic's PCIe/DMA solutions are optimal for minimizing latency. Similarly, in datacenter applications, PCIe solutions typically interface processors with network and storage devices. Algo-Logic's PCIe solutions and Ethernet IP cores can be used in low latency in-memory database applications such as the Key-Value Search (KVS).

The Register Interface supports a low latency host to FPGA communication through memory-mapped I/O (MMIO) with write combining. The DMA Engine is specifically designed for kernel-bypass Linux applications that require high throughput and low latency. The DMA Engine functions include:

  1. Data transfer to implement zero-copy ring buffers memory mapped to user-space
  2. FPGA that advertises data arrival to the descriptor ring buffer
  3. Software API that polls from the descriptor ring buffer to detect data arrival, size, and location in the ring buffer

Algo-Logic's PCIe/DMA solutions are plug-and-play. The hardware interfaces and software APIs are suitable for software developers building low latency network streaming applications. Some of the applications and use-cases include:

  • Rapid data transfer to meet low latency HFT and datacenter gateware application requirements
  • Low latency host OMS to FPGA data transfers to enable user-space controlled High Frequency Trading
  • Four high bandwidth 256-bit wide Rx/Tx datapaths user interface selectable clock frequency of up to 250 MHz
  • Low latency kernel bypass network interface and FPGA Endpoints for ultra-low-latency system requirements
  • Heterogeneous coherent computing with FPGA logic, processors, network storage devices, system memory, and host software applications

Algo-Logic's PCIe/DMA solutions' key features include:

  • Easy to use C/C++ API with four independent Tx/Rx interfaces
  • Parallel tasking support for multiple threads
  • Standard Avalon streaming interface for seamless integration with network logic
  • DMA Engine to provide fastest transfer of data from FPGA logic to software
  • Polling and Ring Buffer DMA architecture

Algo-Logic's PCIe/DMA solutions can be integrated with other components of Algo-Logic's Gateware Defined Networking (GDN) products such as the Tick-to-Trade System, Key Value Search (KVS) in-memory database, as well as with client applications that perform N-Tuple packet classification and Network Function Virtualization (NFV).

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