David Buechner, VP, Impulse Accelerated Technologies
"The Intilop IP core performs the TCP/IP functions and interfaces with Impulse or user logic via a very simple user data FIFO interface."
Impulse Accelerated Technologies and Intilop Corporation have announced an agreement to interface each company's IP to create a portable, FPGA-based TCP stack plus client logic system. This system will enable internet connected appliances to parse, filter, trade, and process streaming data at 10 Gb/s, for a 10X speed advantage over many software based solutions. Effectively, data over the network comes in, TOE accelerates TCP connections, and Impulse C is used to create hardware deployed filters, convolutions, encryptors, financial packet "sniffers" or any other process which requires low latency and limited jitter impact. Moving these applications into hardware, closer to the network stream relieves the host processor, significantly reduces latency and jitter, and opens up multiple possibilities.
Latency and jitter are growing concerns in financial markets, where they are thought to have contributed to the market volatility of the past 2 years. Jitter in this context refers to the inability of the processes sitting behind the stream to keep up with volume spikes. Unlike other streams, the financial stream does not forgive any data drop out and requires a deterministic, scalable processing architecture to be able to neutralize latency. The Impulse/Intilop architecture enables processing on FPGA, and results returned over TCP/IP, without host intervention, jitter or an O/S.
This Smart Programmable TOE architecture implements a full TCP/IP stack including control plane and data plane processing, and preprocesses the streams to offload the host. The combined tool set provides a TCP/IP data stream for any type of Ethernet based streaming data. Where the data would traditionally have gone to a microprocessor, the Impulse C processes "see" and pre-filter the data before the host does. In this way, the network connection and packet processing is achieved in FPGA hardware, in real time, at 10G bit rates without the host. Pilot users of hardware accelerated programmable NICs are using them for encoding, encrypting, or for financial packet sniffing and processing. Other functions that fit this model include parsing, filtering, and normalizing data streams. C programmable NIC software moves hardware closer to the network stream, and provides opportunity to more easily add client trading or analytic logic, accelerating automated trading.
"Well defined interfaces help engineers integrate this solution into their system." Explained David Buechner, VP of Impulse. He continued, "The Intilop IP core performs the TCP/IP functions and interfaces with Impulse or user logic via a very simple user data FIFO interface. Control can be invoked by HDL or C. The data FIFO lines up well with Impulse C co_streams."
"You get direct access to the TCP/IP stream and can program the hardware to act on that stream." said Kelly Massood, CTO of Intilop. "Each TCP/IP socket can be broken off to an individual process [an Impulse co_stream] such that additional processes can be added, resulting in the lowest latency from wire to seeing the data, because it is all on one FPGA."